The field of the invention is that of integrated circuits having DRAM arrays of trench capacitor cells.
Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge and a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Because cell size determines chip density, size and cost, reducing cell area is one of the DRAM designer's primary goals. Reducing cell area is done, normally, by reducing feature size to shrink the cell.
Besides shrinking the cell features, the most effective way to reduce cell area is to reduce the largest feature in the cell, typically, the area of the storage capacitor. Unfortunately, the capacitor plate area reduces capacitance and, consequently, reduces stored charge. Reduced charge means that what charge is stored in the DRAM is more susceptible to noise, soft errors, leakage and other well known DRAM problems. Consequently, another primary goal for DRAM cell designers is to maintain storage capacitance while reducing cell area.
One way to accomplish this density goal without sacrificing storage capacitance is to use trench capacitors in the cells. Typically, trench capacitors are formed by etching long deep trenches in a silicon wafer and, then, placing each capacitor on its side in the trench, orienting the capacitors vertically with respect to the chip's surface. Thus, the surface area required for the storage capacitor is dramatically reduced without sacrificing capacitance, and correspondingly, storable charge.
However, since using a trench capacitor eliminates much of the cell surface area, i.e., that portion of cell area which was formerly required for the storage capacitor, the cell's access transistor has become the dominant cell feature determining array area. As a result, to further reduce cell and array area, efforts have been made to reduce access transistor area, which include making a vertical access transistor in the capacitor trench. See, for example, U.S. Pat. No. 6,426,252 entitled “Silicon-On-Insulator Vertical Array DRAM Cell With Self-Aligned Buried Strap” and references cited in it.
Performance is equally as important as density to DRAM design. Silicon-on-insulator (SOI) has been used to decrease parasitic capacitance and hence to improve integrated circuit chip performance. SOI reduces parasitic capacitance within the integrated circuit to reduce individual circuit loads, thereby improving circuit and chip performance. However, reducing parasitic capacitance is at odds with increasing or maintaining cell storage capacitance. Accordingly, SOI is seldom used for DRAM manufacture. One attempt at SOI for DRAMS is taught in the cited patent.
Thus, there is a need for increasing the number of stored data bits per chip of Dynamic Random Access Memory (DRAM) products. There is also a need for improving DRAM electrical performance without impairing cell charge storage.
Referring now to the drawings, and more particularly, FIG. 7 shows a flow diagram of a prior art silicon-on-insulator (SOI) process for forming vertical DRAM cells in the cited patent. First, in step 100, a layered semiconductor wafer is prepared. Preferably, the initial wafer is a single crystal silicon wafer. A buried oxide (BOX) layer is formed in the silicon wafer. The BOX layer isolates a silicon layer (SOI layer) above the BOX layer from a thick substrate, which is much thicker than the silicon layer. Then, in step 102 deep trenches are formed, preferably, using a typical photolithographic and etch process. The deep trenches are formed through the silicon layer, the BOX layer and into the thicker substrate. A thin node dielectric layer is conformally formed on the wafer and along the deep trench sidewalls. After forming the thin node dielectric layer a capacitor plate is formed in step 104 in the deep trenches. Then, in step 106, the thin node dielectric layer is stripped from the SOI layer and the upper portion of the BOX layer sidewalls are recessed around the upper surface of each of the capacitor plates.
Next, in step 108, the recesses are filled with conductive strapping material. Then, in step 110, oxide is formed on the wafer and, especially, on top of the capacitor plate, i.e., trench top oxide (TTO) is formed. In step 112 excess TTO is stripped from the wafer surface. In step 114 the pad nitride layer is removed from the wafer surface and gate oxide is formed on the trench sidewalls. In step 116 access transistor gates are formed along the trench sidewalls and cells are defined using shallow trench isolation techniques. Finally, in step 118, cell definition is completed by defining device regions and device wells and forming bit lines and word lines. FIG. 8 illustrates a completed vertical DRAM cell in a deep trench according to the steps of FIG. 7. First, as noted above, the BOX layer 822 is formed in a single crystal silicon wafer. The BOX layer 822 separates the SOI silicon layer 824 from the remaining thicker silicon substrate 826. Although the BOX layer 822 is formed, preferably, using a high-dose oxygen ion implantation in the single crystal wafer, any other suitable SOI technique may be employed. The preferred BOX layer 822 thickness is 300 nm, but the BOX layer 822 may be 10 nm to 500 nm thick. BOX layer 822 thickness may be selected by adjusting ion implantation dose and energy. The SOI silicon layer 824, preferably, is 500 nm thick. However, the SO layer 824 may be 100 nm to 1000 nm thick depending on the desired cell access transistor channel length and SOI layer 824 thickness may be adjusted using chemical vapor deposition (CVD) epitaxial growth. Having prepared the layered wafer, memory cells may be formed on the wafer or the wafer may be stored for future use.
Preferred embodiment DRAM cell formation continues by forming a pad layer of an insulating material such as silicon nitride (SiN) on the upper surface of silicon layer 824. The pad layer may be formed using low-pressure CVD (LPCVD), for example, to deposit a 10 nm to 500 nm, preferably 200 nm, thick SiN layer. Optionally, prior to forming the pad LPCVD SiN layer, a thin (2 nm to 10 nm, preferably 5 nm) thermal oxide layer (not shown) may be formed on the surface of SOI silicon layer 824.
Having prepared the wafer in step 100, deep trenches 820 are opened through the SOI layer 824, BOX layer 822 and into the substrate 826 in step 102. A hard mask layer (not shown) of boron silicate glass (BSG) is formed on the SiN pad layer. Alternatively, any suitable hard mask material such as undoped silicate glass (USG) may be used for the hard mask layer. The deep trenches are formed using a conventional photolithography technique to pattern the BSG hard mask layer and then the trenches are etched using an anisotropic dry technique, such as Reactive Ion Etch (RIE). Preferably, the deep trenches extend 6 μm into substrate 826 but, may extend 3 μm to 10 μm into the substrate 826.
The storage capacitor counter-electrode, i.e., the common capacitor plate surrounding the trench, is formed, preferably, by doping the substrate 824 with a relatively high concentration of an appropriate n-type dopant. Alternatively, the substrate may be un-doped and, after etching the trenches, the substrate 826 trench sidewalls may be doped appropriately and, the dopant is outdiffused into the substrate 826 to form the counter-electrode. After forming the trenches and, if necessary, the counter-electrode a thin (25–60 Angstrom) node dielectric layer 832 is formed, preferably an LPCVD SiN layer, which is the storage capacitor dielectric.
Next, in step 104, a capacitor plate 834 is formed in trenches. The capacitor plate 834 is formed by depositing a doped polysilicon (poly) layer using LPCVD, preferably doped with n-type dopant. Then, the doped polysilicon layer is planarized to the pad layer and recessed into the deep trench to a point beneath the SOI layer 824 and within the BOX layer 822, preferably, using an isotropic dry etch such as an SF6 plasma.
The thin node dielectric 832 is stripped from SOI and BOX trench sidewalls and, recesses are formed in the BOX that will be filled with conductive material to form straps 844. The thin node dielectric 832 is stripped from the trench sidewalls, preferably, using a wet etch such as hydrofluoric acid, which exposes SOI layer 824 sidewalls and the upper edge of BOX layer 822. Then, the exposed sidewall portion of BOX layer 822 is isotropically etched, preferably using a wet solution containing HF to form recesses beneath exposed sidewalls. The etch time is selected such that the oxide removal does not expose the top of substrate 826 and, the recess is contained within the BOX layer 822. Thus, the recesses are bounded at the top by SOI layer 824 and on one side by thin node dielectric layer 832 along upper end of trench capacitor plates 834. So, subsequent to forming the recesses, a wet strip is used to etch exposed thin node layer 832 material from within the recesses, exposing the upper end of trench capacitor plates 834 therein.
Next, an interfacial treatment of a thin dielectric surface layer (not shown), such as a 7 Angstrom oxide or nitride layer, is formed on SOI sidewalls 838, 840 and on the exposed upper surface 842 of polysilicon plate 834. This thin, 7 Angstrom dielectric interfacial treatment layer controls and limits the extent of outdiffusion from the polysilicon plate 834 into SO layer 824. Thus, the thin dielectric interfacial treatment layer is not completely isolating, but is electrically conductive for electron tunneling along the side of polysilicon plate 834 and at the underside of SOI layer 824.
In step 108 a thin strap layer is deposited and excess strap material is removed leaving straps 844. The thin strap layer, which is of sufficient thickness to completely fill the recesses, preferably is 30 nm thick and may be 10–50 nm thick. The strap layer is formed using LPCVD to deposit the desired thickness of doped polysilicon. Then, the excess strap material is selectively removed from horizontal and vertical surfaces, the remaining polysilicon strap material forming straps 844. Any suitable selective wet etch or dry etch with selectivity to the interfacial treatment of the exposed SOI sidewalls may be used to remove the excess strap material. Thus, when dopant is subsequently outdiffused into SOI layer 824, the straps 844 form a self-aligned buried electrical connection between the trench polysilicon capacitor plate 834 and the SOI layer 824 thereabove.
In step 110 an oxide layer is formed on the wafer, forming trench-top-oxide (TTO) 848 on capacitor plates 834. Preferably, an anisotropic high density plasma (HDP) is used to deposit the TTO layer 848. HDP has a high deposition rate along the horizontal surfaces, and a slow deposition rate along vertical surfaces such as the sidewalls.
Then, excess surface oxide layer is removed from the pad SiN surface in step 112. Photoresist plugs are formed in trenches on TTO 848. Preferably, a photoresist layer is deposited and etched back such that only photoresist plugs remain in the trenches. The excess surface oxide is removed using an appropriate etch such as RIE. Then, the photoresist plugs are removed. Optionally, the excess surface oxide layer may be removed using a typical selective chemical mechanical polishing (CMP) step that is selective to nitride.
Next, the pad SiN is removed and gate oxide is formed in step 114. The pad SiN layer is removed using an appropriate etchant and a 5–20 nm sacrificial oxide layer, preferably 80 nm, is grown by thermal oxidation. The sacrificial oxide layer (not shown) repairs superficial surface damage that may have occurred in the exposed SOI layer 824 and sidewalls. Selected device regions are defined in the wafer and are doped using ion implantation. The sacrificial oxide layer is stripped using a hydrofluoric acid solution. Then, a 2–100 nm gate oxide layer, preferably 5 nm, is grown on the SOI layer 824 using thermal oxidation.
Cell access transistor formation is completed in step 116. A gate conductor (GC) 854 is formed, filling trenches, preferably, using LPCVD to deposit a polysilicon layer. A protective nitride pad layer (not shown) is deposited on the polysilicon layer. Then, a device isolation trench 856 is formed using a conventional shallow trench isolation (STI) process, such as conventional photolithography and dry etching, e.g., RIE. The RIE formed shallow trenches remove one deep trench sidewall and extends down through the SOI silicon layer 824, BOX layer 822 and into substrate 826. Thus, the shallow trenches 856, essentially, form isolated silicon islands of SOI layer 824 on BOX layer 822 with a gate conductor 854 remaining along one sidewall 838, thereby forming each cell's access gate. Then, the shallow trenches 856 are filled with a dielectric material such as silicon dioxide using a process such as an anisotropic HDP deposition. Then, the surface is planarized to the protective SiN pad surface using a conventional CMP process. The protective SiN pad is stripped from the wafer using a standard wet etch. A polysilicon wordline layer is formed on the surface in contact with the gate conductor 854 and patterned, using lithography and dry etching.